1. Field of the Invention
The present invention relates to a method and an apparatus for regenerating a sampling frequency and then quickly locking signals accordingly, more particularly to, a method and apparatus for regenerating a sampling frequency and then quickly locking signals in a digital multimedia system.
2. Description of the Prior Arts
For reducing distortion and avoiding letting signal lines twisting in home, it is inevitable for home video/audio electric appliances to adopt digital audio technology systems. In the conventional art, optical fibers are used for digital signal transmission, where its drawback is its high cost. But audio and video are integrated into the same interface in the digital multimedia system, hence the conventional AV terminals are mostly replaced and thus a high quality performance is provided.
It is very complicated to discuss the transmission of the digital audio in the technology domain. First of all, there are so many complicated details troubling the engineers, such as the number of audio channels, data formats, sampling frequencies, compressed or not, and one bit audio. Second, in the digital multimedia system such as HDMI is transmitted by packets, thus the engineers must have knowledge regarding transmission mechanism. Further, in the film, there must be no error in the synchronization between audio and video.
Audio information carried on the linking of the digital multimedia system such as HDMI, can merely rely on TMDS, that is, the video clock. In other words, there will not contain or reserve the sampling frequency of original audio during data transmission. Hence, the sink side must regenerate the sampling frequency, and such kind of action is called “Audio Clock Regeneration”. This concept is well applicable in any I/O standards such as USB, DisplayPort, IEEE 1394 and so on. The critical point is which methodology is adopted for achieving the regeneration.
Referring to FIG. 1, which provides a possible embodiment, a receiving apparatus 10 for locking signals, which comprises a first dividing means 101, a second dividing means 102, and a phase-locking loop 103.
In most of the digital multimedia systems, in the source of the audio, the clocks of its audio and video are generated by a common clock source, and this configuration is called “Coherent Clocks.” In such a situation, there exists a numerical relationship between them, that is to say; between the clocks they can be divided by one another without remainder. The essential concept of the aforesaid system is that the source apparatus of the audio must calculate the fractional number between the video clock and the audio clock.
To give an example as HDMI, as shown in FIG. 1, the video clock and the audio clock exhibits a mathematical relationship as follows: 128*fs=fTMDS—CLOCK*N/CTS (In DisplayPort, the equation will be write as 512*fs=fTMDS—CLOCK*Maud/Naud). Apparently, the source apparatus of the audio have to decide the N at numerator side and the Cycle Time Stamp (CTS) at denominator side, the value of N/CTS (or Maud/Naud) is transmitted by data from the source side for providing the parameters for the first dividing means 101 and the second dividing means 102. In case that the video and audio signals are synchronized to each other, then CTS can be treated as fixed. If not synchronized, means that signal jitters are exist, hence CTS may change. FIG. 1 illustrates that the corresponding parameters N and CTS are transmitted via Audio Clock Regeneration packets to the sink side, and the video clock is carried via the TMDS Clock Channel.
The above mentioned conventional art has drawback at least as follows:
(1) The corresponding parameters N and CTS are transmitted via Audio Clock Regeneration packets to the sink side, hence, the phase-locking loop 103 can not start the locking procedure until the Audio Clock Regeneration packets arrived and all the parameters of the packet are deciphered, which leads to the slower response time.
(2) When the Audio Clock Regeneration packets deliver an incorrect value of N or CTS, incorrect sampling frequency will be determined. Therefore, a processor will mistakenly set up the parameters of corresponding circuit, such as the phase-locking loop 103 and hence send out the incorrect audio signals.
(3) While changing the audio sampling frequency, there will be a period of unresponsive time leads to send out the incorrect voice. In other words, if the audio clocks and video clocks are not synchronization, means that signal jitters are exist, hence CTS may change.
(4) The suggestion values of N and CTS are relatively large, as the table 2a˜2c shown in FIG. 2A˜2C, there are specified audio sampling frequencys such as 32/44.1/48 kHz, which are the most popular frequencys and their corresponding suggestion values for N and CTS. The large value makes the dividing means 101 and 102 cooperated with the locking loop 103 complicated and thus hard to be designed.
(5) The source apparatus have to determine the N at numerator side and the CTS at denominator side, thus the complexity for the source apparatus is increase.
(6) The parameter adjustment for the phase-locking loop 103 must be proceed by the processor, and correspondingly the processor inevitably needs external drivers, hence increase the design complexity and manufacturing cost.
In DisplayPort standard, Maud and Naud are respectively corresponding to N and CTS, since there exist the same issues, redundant information will be thus omitted.
Accordingly, in view of the above drawbacks, it is an imperative that an apparatus and method are designed so as to solve the drawbacks as the foregoing.